Reliability Study of High-Pin-Count Flip-Chip BGA

A family of 1.0-mm pitch full-array flip-chip BGAs were developed. These packages vary from 27 to 45 mm in package size, 15 to 25 mm in die size, and 672 to 1020 in ball count. With dies and packages so large, solder joint fatigue failure and underfill delamination, induced by thermal expansion mismatch, are a major concern. Finite element analysis was set up for efficient reliability analysis. Two substrates, hi-CTE ceramic (12x10 /oC) and BT (17x10 /oC), are compared. Hi-CTE ceramic substrate has a better CTE match with die (2.6x10 /oC), therefore, it was surmised that hi-CTE ceramic would improve component-level reliability yet with satisfactory board-level reliability. To validate it, several die and package combinations were modeled using both substrates. Both component-level stresses and board-level solder joint fatigue life were compared. In addition, design of experiment (DOE) was used to study the effect of properties and dimensions of underfill and heat spreader on solder joint fatigue life. The effect of pad opening size was also quantified. Finally, the effect of underfill on interface stress between underfill and die was investigated. Introduction In high-end logic devices, high I/O count, high speed and high power dissipation are the major requirements. Flip-chip BGA offers an effective package solution as it can provide such features [1-2]. A family of 1.0-mm pitch flip-chip BGAs were developed to provide these high-performance devices. These packages vary from 27mm to 33mm in size with die size from 15mm to 25mm and a full grid array of solder balls from 600 to 1200. With such large dies and packages, underfill delamination and solder joint fatigue failures induced by thermal expansion mismatch become a major concern. The key to reducing underfill delamination is to improve interfacial integrity between die, underfill and substrate. The important factors are surface treatment of the die and substrate, underfill properties including adhesion strength, flow characteristics, void formation, cure kinetics, and reflow process [3-9]. Finite element analysis was used for efficient reliability evaluations. Two substrates, hi-CTE ceramic (12x10 /oC) and BT (17x10 /oC), were compared. Hi-CTE ceramic substrate has a better CTE match with die (2.6x10 /oC), so it was speculated that it could improve component-level reliability yet with satisfactory board-level reliability. To validate it, several die and package combinations were modeled using both substrates. Both component-level stresses and board-level solder joint fatigue life were predicted. Based on the results, BT substrate was selected. Seven factors were chosen for a DOE study. These factors included the dimensions and the material properties of heat spreader and underfill. The significance of each factor was determined by analysis of variance (ANOVA). The package pad opening size was found to have great effect on solder joint life. Effect of Underfill on the interface stress between die and underfill was also investigated. The results will be presented in the paper. Flip-chip BGA The structure of this package is shown in Figure 1. A heat spreader (HS) was attached to the die to improve power dissipation capability. A fin can be attached to the heat spreader to dissipate more heat in higher power applications. Solder bumps can be either eutectic 63Sn37Pb or high-lead 95Pb5Sn. Solder ball layout is a full array of 1.0mm pitch. The solder balls are 0.63 mm in diameter. The nominal height of the package is 3.2 mm, in compliance with the JEDEC (Joint Electron Device Engineering Council) Standard [10]. Figure 1 A Cross-sectional View of the Flip-chip BGA Finite Element Modeling The modeling methodology and the life prediction model from [11] were adopted to predict solder joint fatigue life. Because of the high homologous temperature (ratio of operating and melting temperatures in absolute scale) and slow strain rates in actual service conditions, time dependent creep is the primary deformation mode for eutectic solder joints. Grain boundary sliding and matrix creep are the major deformation mechanisms considered in this methodology. Readers are referred to [11] for details. ANSYS [12] was used for finite element analysis. The modeling approach is as follows: A one-quarter symmetric model of the package was developed using eight-node 3-D brick elements, as shown in Figure 2. This model was first analyzed using linear elastic analysis to determine the location of the solder joint failing first. The joint at that location was removed from the model and the rest of the package was Die HS